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verilog-i2c: Verilog I2C Interface

This repository provides Verilog implementations of I2C master and slave interfaces. It includes various module types with AXI and Wishbone interfaces for flexible FPGA integration. The project is deprecated in favor of fpganinja/taxi.
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This project provides a collection of Verilog modules for implementing I2C (Inter-Integrated Circuit) communication. It supports both master and slave roles, offering different interface options like AXI and Wishbone. The modules are designed for easy integration into FPGA designs, facilitating communication with I2C peripherals. The primary technology used is Verilog hardware description language.

This project offers a variety of I2C master and slave implementations tailored to different interface requirements (AXI, Wishbone). It includes comprehensive testbenches using MyHDL for simulation and verification. The designs are modular and well-documented, promoting code reuse and adaptability within FPGA projects.

  • Multiple Interfaces: Supports AXI, Wishbone, and other interfaces for integration with various FPGA architectures.
  • Comprehensive Testbenches: Includes MyHDL testbenches for robust simulation and verification of I2C communication.
  • Modular Design: Modules are designed to be independent and reusable within different FPGA designs.
  • Parametrizable Interfaces: Wishbone interfaces are parametrized for flexible configuration of master/slave width.
  • AXI Stream Support: AXI stream interfaces allow for efficient data transfers.
  • Complete I2C Stack: Covers necessary components like initialization, master control, and slave responses.
  • Well-Documented: Includes explanations and examples for ease of use.

The repository is currently archived and no longer actively maintained. The project provides a foundational set of I2C modules that have been used in various FPGA projects. Documentation is present, though potentially outdated given the deprecation. While the code itself is functional, it is recommended to migrate to the Taxi project for future development and support.

This project provides Verilog implementations for I2C interfaces, benefiting FPGA developers who need to integrate with I2C devices. It simplifies the implementation of I2C master and slave functionalities, offering flexible interface options. Due to its deprecated status, consider using the fpganinja/taxi repository for new projects.

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Created
12 years ago
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Updated 17 days ago

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